TSMC’s N2 Technology – IEEE Spectrum

TSMC explained its next-generation transistor technology at the IEEE International Electron Device Meeting (IEDM) in San Francisco this week. N2 (two nanometer) technology is the semiconductor manufacturing giant’s first foray into a new transistor architecture called nanosheet or gate-all-around.

Samsung has the process to make similar devices, and Intel and TSMC both plan to produce them in 2025.

Compared to TSMC’s most advanced process today, N3 (3 nanometers), this new technology offers up to 15 percent faster speeds or up to 30 percent more energy efficiency, while increasing density by 15 percent. Achieve improvements.

N2 is “the culmination of more than four years of hard work,” Jeffrey Yeap, TSMC’s vice president of research, development and advanced technology, told IEDM engineers. Today’s transistors, FinFETs, have a vertical fin of silicon in the center. Nanosheet or gate-all-around transistors instead have a stack of thin silicon ribbons.

This difference not only allows for better control of the current flowing through the device, but also allows engineers to fabricate a greater variety of devices by making the nanosheets wider or narrower. FinFETs can only provide that versatility by increasing the number of fins in the device, such as devices with one, two, or three fins. But nanosheets offer designers options for gradations between them, such as the equivalent of 1.5 fins or those suitable for specific logic circuits.

TSMC’s technology, called Nanoflex, allows for different logic cells built with different nanosheet widths on the same chip. Logic cells made from narrower devices make up the general logic on a chip, while logic cells with wider nanosheets that can drive more current and switch faster make up the CPU core. .

The flexibility of nanosheets has a particularly significant impact on SRAM, the primary on-chip memory in processors. This critical circuit, consisting of six transistors, has not shrunk as quickly as other logic over several generations. However, the N2 appears to have broken through this set of scaling stagnations, resulting in what Yeap describes as the densest SRAM cell ever, delivering 38 megabits per square millimeter, compared to the previous technology, the N3. improved by 11 percent. N3 achieved only a 6% improvement over its predecessor. “SRAM captures the inherent benefit of doing a gate-all-around,” Yeap says.

Future gate all-round transistor

While TSMC announced details about next year’s transistors, Intel focused on how quickly the industry can shrink transistors. Intel’s answer: Longer than originally thought.

“Nanosheet architecture is really the last frontier for transistor architecture,” Ashish Agrawal, a silicon engineer in Intel’s Component Research Group, told Engineers. Even future complementary FET (CFET) devices, likely to arrive in the mid-2030s, will be composed of nanosheets. Therefore, it is important for researchers to understand its limitations, Agrawal said.

“We haven’t hit a wall. It’s doable and this is the proof…We’re really making pretty good transistors.” —Sanjay Natarajan, Intel

Intel has proven that transistors with gate lengths of 6 nanometers work well. intel

Intel investigated an important scaling factor: gate length (the distance covered by the gate between the source and drain of a transistor). The gate controls the current flowing through the device. Gate length reduction is important to reduce the minimum distance between devices in standard logic circuits, known for historical reasons as contact poly pitch (CPP).

“CPP scaling is primarily determined by gate length, but is predicted to stall at a gate length of 10 nanometers,” Agrawal said. The 10-nanometer gate length was particularly problematic because it was so short that it was thought that too much current would leak across the device when it was supposed to be off.

“So we looked at pushing it below 10 nanometers,” Agrawal said. Intel has modified the common gate-all-around structure so that the device only has a single nanosheet through which current flows when the device is on.

By thinning the nanosheets and changing the surrounding materials, the researchers were able to fabricate a device with a gate length of just 6 nm and a nanosheet thickness of just 3 nm, with satisfactory performance. did.

Researchers predict that silicon-gate all-around devices will eventually reach their scaling limits, so researchers at Intel and elsewhere are working to replace the silicon in nanosheets with 2D semiconductors such as molybdenum disulfide. There is. But the 6-nanometer result means those 2D semiconductors may not be needed for some time.

“We haven’t hit a wall yet,” says Sanjay Natarajan, senior vice president and director of technology research at Intel Foundry. “It’s doable, and this is the proof…we’re making really pretty good transistors with a channel length of 6 nanometers.”